1. Field of the Invention
The present invention relates to a baseband demodulator which is installed in a communication equipment based on a digital modulation system to demodulate a baseband signal and more particularly, to a clock synchronization circuit which extracts a phase component from a demodulation timing clock signal and performs phase correction control over a judgement timing clock signal to reduce a judgement error rate of demodulated data, and also to a clock synchronizing method thereof.
2. Description of the Related Art
As known, in such a 4-value digital modulation system as quadrature phase shift keying (QPSK), when it is desired to demodulate a detected signal into a digital value, judgement must be done at correct timing conforming to a modulation frequency.
To this end, it is common practice to divide a clock signal of a demodulator with respect to frequency to generate a judgement timing clock signal. However, since the clock signal of the demodulator is shifted from a clock signal of a modulator with respect to frequency, it becomes necessary to subject the judgement timing clock signal to a phase correction in order to maintain the correct demodulation timing.
For this purpose, a modulator side modulates a bit timing recovery (BTR) pattern and sends it to a demodulation side to inform the demodulator of the demodulation timing; whereas, the demodulation side detects the BTR pattern signal to obtain a BTR pattern detection signal and detects a phase error in the judgement timing clock signal on the basis of the BTR pattern detection signal.
FIG. 12 is a circuit diagram of an exemplary prior art baseband demodulator which includes a clock synchronization circuit for performing phase correction control over the aforementioned judgement timing clock signal.
In the drawing, 8-bit analog/digital converters (which will be referred to merely as the A/D converters, hereinafter) 41 and 42 function to sample orthogonal baseband signals a and b received from a radio frequency (RF) receiver 21 based on a clock signal n corresponding to 8 times the modulation rate (represented by 8fb) to output 8-bit digital data signals c and d respectively.
A delay detector 43 detects the aforementioned data signals c and d at a period of 1/8fb and outputs 8-bit detection data signals e and f.
A judger 44 judges the detection data signals e and f received from the delay detector 43 based on a judgement timing clock signal l to demodulate a 2-value or binary data signal g.
Reference numeral 46a denotes a band pass filter tuned to a modulation frequency. When the detection output signals e and f of the delay detector 43 contain the BTR pattern, the band pass filter 46a has such an operational characteristic that the filter provides a large output, because the detection waveform of the BTR pattern signal has a strong modulation frequency component.
As methods for providing an input to the band pass filter 46a, there are considered methods for inputting either one of the above detection outputs e and f to the filter and for inputting a calculated signal (e-f) to the filter to further improve an S/N ratio.
A phase error detector 47a extracts a demodulation timing (BTR pattern) from the detection output on the basis of an output signal i received from the band pass filter 46a to detect an error with respect to the current judgement timing clock signal l.
A clock reproducer 48 changes the phase of a clock signal having a frequency fb produced at a frequency divider 49 by frequency-dividing a clock signal k applied from the oscillator 5, on the basis of an error signal j received from the phase error detector 47a and outputs its changed result as the judgement timing clock signal l (having the frequency fb).
The clock reproducer 48 further supplies a sampling clock signal n to be used in the A/D converters 41 and 42 and also a bit rate clock signal m (having a frequency 2fb), as clock signals subjected to a phase control in accordance with the phase of the judgement timing clock signal l.
Meanwhile, in this sort of baseband demodulator, since the phase error of the judgement timing clock signal l greatly affects the error rate of a demodulated bit data signal g, the phase error must be controlled with a certain level of accuracy.
For example, in order to keep an accuracy corresponding to 1/8 of the accuracy of the judgement timing signal, the baseband signals a and b are required to be subjected to a sampling operation with the frequency 8fb, which requires the A/D converters 41 and 42 to be both of a high speed type and also the delay detector 43 to be operated at an operational rate of 8fb.
If A/D converters of a low speed are used and the sampling operation is to be carried out with a clock signal having the frequency of 2fb, because only one half of the accuracy of the judgement timing can be obtained, the error rate of the demodulation bit data g becomes considerably worse.
Further, since the necessity of the maintenance of the above accuracy requires the 8-bit-input, infinite-duration impulse-response (IIR or recursive type) digital band pass filter 46a to have an about-20-bit adder and a delay register and also a constant multiplier is required to be of a 20-bit output type, its circuit is inevitably made large in size.
With such a prior art baseband demodulator as mentioned above, in this way, when it is desired to perform phase control of the judgement timing clock signal with an accuracy of 1/8, the orthogonal baseband signals must be sampled with the frequency of 8fb, the A/D converters must be both of a high speed type and the entire demodulator must be operated at the frequency 8fb, which results in that the power consumption of the demodulator is inevitably increased.
Further, there has been a problem that since the digital band pass filter for processing 8-bit input data must be configured with a register, an adder and a multiplier having a large number of bits, the circuit scale becomes large.